1. Technical Field
Various embodiments generally relate to a data training device, and more particularly, to a technology for improving the precision of write training by using a bit line sense amplifier.
2. Related Art
A semiconductor memory device has continuously been developed to increase the degree of integration and elevate an operation speed. In order to elevate an operation speed, a so-called synchronous type semiconductor memory device which is capable of operating in synchronization with a clock provided from an outside of a memory chip has been disclosed.
A DDR (double data rate) synchronous type memory device adopts a scheme of processing two pieces of data (i.e, 1 bit per piece of data or more) during one clock cycle. In each data input/output pin of a DDR synchronous type memory device, two pieces of data are consecutively inputted and outputted in synchronization with the rising edge and the falling edge of a clock which is inputted from an outside. Accordingly, since it is possible to achieve a bandwidth at least two times broader than a conventional SDR synchronous type memory device without increasing the frequency of a clock, a high speed operation may be realized to a corresponding extent.
In a low power consumption DDR synchronous type memory device which operates with a low power supply voltage, it is important to reduce current consumption. To this end, in the low power consumption DDR synchronous type memory device, an internal clock should be enabled only for an inevitably necessary period so as to reduce operation current.
That is to say, in a conventional low power consumption DDR synchronous type memory device, an internal clock is enabled only for an appropriate time after a command is applied using the setup time of a chip select signal, and is disabled in the other period to reduce operation current. In this regard, only when the rising and falling edges of a data clock are within the valid window of data, a semiconductor memory device may be precisely inputted with the data. However, as the operation frequency of a memory device gradually increases, a chip select signal is applied with setup and hold times that become gradually shorter.
A semiconductor device includes a data training device for receiving predetermined input data and controlling the setup and hold times thereof. When reading and writing data from and to a semiconductor memory device (for example, a DRAM), data training is performed to control the skew between data.
Such a data training device is provided for each piece of data to be inputted, and performs a function of controlling the setup time and the hold time of each piece of data to be within an appropriate range with respect to a clock. Here, data training refers to an operation of tuning and controlling the setup time and the hold time between data and a clock (a data strobe signal).
Nevertheless, even through a setup time and a hold time are precisely set with respect to each data inputted from a data pin, in the event that a semiconductor device operates at a higher speed or a skew occurs in each data channel, the setup time and the hold time of the data are likely to go out of an appropriate range.
In other words, the rising edge and the falling edge of a data clock may not be within the valid window of data due to a physical delay factor in the course of transmitting the data clock and the data. In this case, a semiconductor memory device may be inputted with erroneous data. In particular, as the valid window (UI) of data gradually decreases and an amount of data increases in a high speed operating system, stable data transfer becomes difficult.
As a consequence, in a high speed operation specification, a method has been used, in which data is latched in the output terminal of a DQ buffer without passing through a circuit for controlling a setup time or a hold time. In such a structure, in the case where DQ data is fast and a DQS (a data strobe signal) is slow, write training is required to align the DQ data with a DQS point.